Data hazards occur in pipelined processors when an instruction depends on the result of a previous instruction that has not yet completed. These dependencies can lead to incorrect results and stalls in the pipeline, reducing the overall performance. To overcome data hazards and ensure correct execution, various methods are employed in pipelined systems. Some of the common methods to get rid of data hazards are:
Forwarding (Data Forwarding or Data Hazard Interlock):
Also known as data forwarding or data hazard interlock, this technique enables data to bypass intermediate pipeline stages and directly reach the stages where it is needed, avoiding stalls. Forwarding allows the data produced by one instruction to be forwarded directly to the next instruction that requires it. This way, the instruction that needs the data can use the latest available value without waiting for it to be written back to the register file.
There are typically three types of forwarding:
- Forwarding from the Execute stage to the Execute stage (EX-to-EX forwarding).
- Forwarding from the Memory stage to the Execute stage (MEM-to-EX forwarding).
- Forwarding from the Write Back stage to the Execute stage (WB-to-EX forwarding).
Stalling (Data Hazard Stall):
When forwarding is not possible or insufficient to resolve data hazards, stalling is used to introduce bubbles or stalls in the pipeline. A stall means that the pipeline stages do not progress, and the instruction causing the hazard is delayed until the data is available. This gives time for the dependent instruction to complete its execution and write the result back to the register file.
Stalling can negatively impact performance since it introduces delays in the pipeline, but it ensures correct execution and avoids incorrect results due to data hazards.
Compiler Techniques:
Sophisticated compilers can be designed to optimize the code and rearrange instructions to reduce the likelihood of data hazards. Techniques like loop unrolling, loop pipelining, and instruction scheduling can be used to minimize data dependencies and increase instruction-level parallelism, reducing the chance of data hazards occurring.
Software Pipelining:
Software pipelining is a technique where loops are transformed into overlapping iterations that can be executed in parallel. By carefully scheduling loop iterations and operations within the loop, data dependencies can be minimized, and pipelined execution can be achieved even on architectures that do not have hardware pipelining support.
Compiler Inserted Nops (No-Operation Instructions):
In some cases, the compiler may insert nops (no-operation instructions) to introduce delays intentionally to resolve data hazards. By adding nops, the compiler ensures that the dependent instruction does not begin execution until the data it needs is available, avoiding incorrect results due to data hazards.
Hardware Out-of-Order Execution:
Advanced processors with out-of-order execution capability can dynamically rearrange instructions to avoid data hazards and increase instruction-level parallelism. These processors use complex hardware mechanisms to speculatively execute instructions out of their original order while maintaining the correct program semantics.
