In a smartphone, the length of the main memory address is 16-bits. Its L1 cache size is 2K-byte. This cache uses the LRU replacement algorithm and is organized as a 4-way set-associative cache with 64 bytes per cache line. Consider the memory as word addressable and the size of the word is 1 byte.
i) How many lines are there in the cache?
ii) How many sets are there in the cache?
iii) Calculate the number of bits in each of the Tag, Set, and Word fields of the memory address.
iv) When a program is executed, the processor reads data sequentially from the following word addresses:
128H, 144H, 176H, 180H, 129H, 170H
All the above addresses are shown in hexadecimal values. Assume that the cache is initially empty. For each of the above addresses, indicate whether the cache access will result in a hit or a miss.
Answer:
i) There are 32 lines in the cache
ii) There are 8 sets in the cache
iii) Tag : 7, Set : 3 and word : 6
iv)
128 => 0000 0001 0010 1000 => S4, BLOCK4 == M
144 => 0000 0001 0100 0100 => S5, BLOCK5 == M
176 => 0000 0001 0111 0110 => S5, BLOCK4 == M
180 => 0000 0001 1000 0000 => S6, BLOCK6 == M
129 => 0000 0001 0010 1001 => S4, BLOCK4 == M
170 => 0000 0001 0111 0000 => S5, BLOCK5 == M
