Here we will describe the steps you can follow to design a block diagram for the hardware that implements the statement x + yz: AR <– AR + BR.
- Registers AR and BR: These are your primary registers. Depict each as a rectangle. These are n-bit registers, which means each one stores a binary number with n bits.
- ALU (Arithmetic Logic Unit): Depict an ALU as another rectangle, with two input lines (one from AR and one from BR) and one output line (back to AR). The ALU performs the arithmetic addition operation specified in your expression.
- Control Unit: Depict a control unit as a square, with inputs x, y, and z. The control unit will output a control signal to the ALU based on the logic function x + yz.
- Logic gates: Since x, y, and z are control variables and the “+” signifies an OR operation in a Boolean function, you’ll need an OR gate and an AND gate. The OR gate accepts inputs x and the output of the AND gate. The AND gate accepts inputs y and z. The output of the OR gate will be the control signal for the ALU.
If you follow these steps, you should be able to create a simple block diagram for the hardware implementing the given statement. The flow of information should look like this: AR and BR inputs to ALU, ALU output to AR, and control signals from x, y, and z through the logic gates to the ALU.
